EVAL-AD5761RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5761RSDZ
Analog Devices
'EVAL-AD5761RSDZ' PDF : 35 Pages View PDF
AD5761R/AD5721R
Data Sheet
REGISTER DETAILS
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input,
SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0),
four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively.
Table 8. AD5761R 16-Bit Input Shift Register Format
MSB
LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
X1
X1
X1
0
Register address
Register data
1 X is don’t care.
Table 9. AD5721R 12-Bit Input Shift Register Format
MSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17
X1
X1
X1
0
Register address
1 X is don’t care.
DB16
DB[15:4]
Register data
LSB
DB[3:0]
XXXX1
Table 10. Input Shift Register Commands
Register Address
DB19 DB18 DB17 DB16 Command
0
0
0
0
No operation
0
0
0
1
Write to input register (no update)
0
0
1
0
Update DAC register from input register
0
0
1
1
Write and update DAC register
0
1
0
0
Write to control register
0
1
0
1
No operation
0
1
1
0
No operation
0
1
1
1
Software data reset
1
0
0
0
Reserved
1
0
0
1
Disable daisy-chain functionality
1
0
1
0
Readback input register
1
0
1
1
Readback DAC register
1
1
0
0
Readback control register
1
1
0
1
No operation
1
1
1
0
No operation
1
1
1
1
Software full reset
Rev. C | Page 28 of 36
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