EVAL-AD5761RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5761RSDZ
Analog Devices
'EVAL-AD5761RSDZ' PDF : 35 Pages View PDF
Data Sheet
Synchronous DAC Update
In synchronous DAC update mode, LDAC is held low while
data is being clocked into the input shift register. The DAC
output is updated on the rising edge of SYNC.
Asynchronous DAC Update
In asynchronous DAC update mode, LDAC is held high while
data is being clocked into the input shift register. The DAC output
is asynchronously updated by taking LDAC low after SYNC is
taken high. The update then occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5761R/AD5721R can be reset to their power-on state
by two means: either by asserting the RESET pin or by using the
software full reset registers (see Table 26).
Asynchronous Clear Function (CLEAR)
The CLEAR pin is a falling edge active input that allows the
output to be cleared to a user defined value. The clear code
value is programmed by writing to Bit 10 and Bit 9 in the
control register (see Table 11 and Table 12). Maintain CLEAR
low for the minimum time of 20 ns to complete the operation
(see Figure 2). When the CLEAR signal is returned high, the
output remains at the clear value until a new value is loaded to
the DAC register.
Alert Function (ALERT)
When the ALERT pin is asserted low, a readback from the control
register is required to clarify whether a short-circuit or brownout
condition occurred, depending on the values of Bit 12 and Bit 11,
the SC and BO bits, respectively (see Table 15 and Table 16). If
neither of these conditions occurred, the temperature exceeded
approximately 150°C.
The ALERT pin is low during power-up, a software full reset, or
a hardware reset. After the first write to the control register to
configure the DAC, the ALERT pin is asserted high.
AD5761R/AD5721R
In the event of the die temperature exceeding approximately
150°C, the ALERT pin is low and the value of the ETS bit
determines the state of the digital supply of the device, whether
the internal digital supply is powered on or powered down. If
the ETS bit is set to 0, the internal digital supply is powered on
when the internal die temperature exceeds approximately
150°C. If the ETS bit is set to 1, the internal digital supply is
powered down when the internal die temperature exceeds
approximately 150°C, and the device becomes nonfunctional
(see Table 11 and Table 12).
The AD5761R/AD5721R temperature at power-up must be less
than 150°C for proper operation of the devices.
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient. Thermal hysteresis data
was tested for the AD5761R as shown in Figure 75. It is measured
by sweeping the temperature from ambient to −40°C, then to
125°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements (shown in
Figure 75).
5
4
3
2
1
0
–120
–100
–80
–60
–40
–20
DISTORTION (ppm)
Figure 75. Thermal Hysteresis
Rev. C | Page 27 of 36
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