EVAL-AD5765EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5765EBZ' PDF : 28 Pages View PDF
Data Sheet
TRANSFER FUNCTION
Table 8 shows the ideal input-code-to-output-voltage rela-
tionship for the AD5765 for both offset binary and twos
complement data coding.
Table 8. Ideal Output Voltage to Input Code Relationship
Digital Input
Analog Output
Offset Binary Data Coding
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Twos Complement Data Coding
MSB
LSB
0111 1111 1111 1111
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
VOUTx
2 VREF × (32,767/32,768)
2 VREF × (1/32,768)
0V
−2 VREF × (1/32,768)
−2 VREF × (32,767/32,768)
VOUTx
2 VREF × (32,767/32,768)
2 VREF × (1/32,768)
0V
−2 VREF × (1/32,768)
−2 VREF × (32,767/32,768)
AD5765
The output voltage expression for the AD5765 is given by
VOUT
= −2 ×VREFIN
+
4
× V REFIN


D
65,536


where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB and
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 2) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If, at power-on, CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5765.
Table 9. AD5765 Input Register Format
MSB
DB23
DB22
DB21
DB20
R/W
0
REG2
REG1
DB19
REG0
DB18
A2
DB17
A1
DB16
A0
LSB
DB15:DB0
Data
Table 10. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register
REG2 REG1 REG0
Function
0
0
0
Function register
0
1
0
Data register
0
1
1
Coarse gain register
1
0
0
Fine gain register
1
0
1
Offset register
A2, A1, A0
Used to decode the DAC channels
A2
A1
A0
Channel Address
0
0
0
DAC A
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
All DACs
D15:D0
Data bits
Rev. C | Page 19 of 28
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