EVAL-AD7982SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7982SDZ' PDF : 26 Pages View PDF
AD7982
Data Sheet
THEORY OF OPERATION
IN+
REF
GND
MSB
SWITCHES CONTROL
LSB SW+
131,072C 65,536C
4C
2C
C
C
131,072C 65,536C
4C
2C
C
C
COMP
CONTROL
LOGIC
BUSY
OUTPUT CODE
MSB
LSB SW–
CNV
IN–
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7982 is a fast, low power, single-supply, precise 18-bit
ADC using a successive approximation architecture.
The AD7982 is capable of converting 1,000,000 samples per
second (1 MSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it typically consumes
70 μW, making it ideal for battery-powered applications.
The AD7982 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7982 can interface to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead
LFCSP that allows space savings and flexible configurations.
It is pin for pin compatible with the 16-bit AD7980.
CONVERTER OPERATION
The AD7982 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via Switch SW+
and Switch SW−. All independent switches are connected to
the analog inputs. Therefore, the capacitor arrays are used as
sampling capacitors and acquire the analog signal on the IN+
input and the IN− input. When the acquisition phase
completes and the CNV input goes high, a conversion phase
initiates. When the conversion phase begins, SW+ and SW− open
first. The two capacitor arrays then disconnect from the inputs
and connect to the GND input. Therefore, the differential
voltage between the IN+ and IN− inputs captured at the end of
the acquisition phase applies to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 … VREF/262,144). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of the
conversion phase process, the device returns to the acquisition
phase and the control logic generates the ADC output code and
a busy signal indicator.
Because the AD7982 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. E | Page 14 of 26
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