EVAL-AD7982SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7982SDZ' PDF : 26 Pages View PDF
Data Sheet
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
CS mode, 3-wire without busy indicator is usually used when a
single AD7982 is connected to an SPI-compatible digital host.
The connection diagram is shown in Figure 28, and the
corresponding timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion is initiated, it continues until
completion irrespective of the state of CNV. This feature can be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
AD7982
When the conversion completes, the AD7982 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the 18th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
CNV
VIO
SDI AD7982 SDO
CONVERT
DIGITAL HOST
DATA IN
SDI = 1
tCNVH
CNV
SCK
CLK
Figure 28. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
tCYC
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCKL
tSCK
SCK
1
2
3
16
17
18
tHSDO
tSCKH
tEN
tDSDO
tDIS
SDO
D17
D16
D15
D1
D0
Figure 29. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. E | Page 19 of 26
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