EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
The procedure typically requires several iterations until an
acceptable compromise is reached. The successful implementation
of a combined LNA/PA matching network for the ADF7025 is
critically dependent on the availability of an accurate electrical
model for the PC board. In this context, the use of a suitable CAD
package is strongly recommended. To avoid this effort, however, a
small form-factor reference design for the ADF7025 is provided,
including matching and harmonic filter components. The design
is on a 2-layer PCB to minimize cost. Gerber files are available
on the www.analog.com website.
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
PREAMBLE
SYNC
WORD
ID
FIELD
DATA FIELD
CRC
Figure 33. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK
demodulation. The recommended preamble pattern is a dc-free
pattern such as a 10101010… pattern. Preamble patterns with
longer run-length constraints such as 11001100…. can also be
used. However, this results in a longer synchronization time of
the received bit stream in the receiver.
Manchester coding can be used for the entire transmit protocol.
However, the remaining fields that follow the preamble header
do not have to use dc-free coding. For these fields, the ADF7025
can accommodate coding schemes with a run-length of up to
six bits without any performance degradation.
If longer run-length coding must be supported, the ADF7025
has several other features that can be activated. These involve a
range of programmable options that allow the envelope detector
output to be frozen after preamble acquisition.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 7 lists the minimum number of writes needed to set up
the ADF7025 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection.
When going from Tx to Rx or vice versa, the user needs to write
only to the N register to alter the LO by 200 kHz and to toggle
the Tx/Rx bit.
Table 7. Minimum Register Writes Required for Tx/Rx Setup
Mode
Registers
Tx
012
Rx (FSK)
0 1 2 4 6 91
Tx to Rx and Rx to Tx 0
1 Register 9 should be programmed in receive mode in order to set the
recommended AGC threshold settings (low = 15, high = 79).
Figure 36 and Figure 37 show the recommended programming
sequence and associated timing for power-up from standby
mode.
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing to the
ADF7025, the ADI ADuC84x microcontroller parts, or the
Blackfin® BF53x DSPs using the hardware connections shown in
Figure 34 and Figure 35.
ADuC84x
ADF7025
MISO
MOSI
SCLOCK
SS
P3.7
P3.2/INT0
P2.4
GPIO
P2.5
P2.6
P2.7
TxRxDATA
RxCLK
CE
INT/LOCK
SREAD
SLE
SDATA
SCLK
Figure 34. ADuC84X to ADF7025 Connection Diagram
ADSP-BF533
SCK
MOSI
MISO
PF5
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
VCC
GND
ADF7025
SCLK
SDATA
SREAD
SLE
TxRxCLK
TxRxDATA
INT/LOCK
CE
VCC
GND
Figure 35. BF533 to ADF7025 Connection Diagram
Rev. A | Page 24 of 44
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