EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
19mA TO
22mA
14mA
3.65mA
2.0mA
XTAL
T0
REG.
READY WR0 WR1
T1 T2 T3
VCO
T4
WR3 WR4 WR6
T5 T6 T7
AGC/
RSSI
T8
CDR
T9
RxDATA
T11
TON
Figure 36. Rx Programming Sequence and Timing Diagram
TOFF
TIME
Table 8. Power-Up Sequence Description
Parameter
T0
T1
T2, T3, T5,
T6, T7
T4
T8
T9
T11
Value
2 ms
10 µs
32 × 1/SPI_CLK
1 ms
150 µs
5 × bit_period
Packet length
Description/Notes
XTAL starts power-up after CE is brought high. This typically depends on the XTAL
type and the load capacitance specified.
Time for regulator to power up. The serial interface can be written to after this time.
Time to write to a single register. Maximum SPI_CLK is 25 MHz.
The VCO can power-up in parallel with the XTAL. This depends on the CVCO
capacitance value used. A value of 22 nF is recommended as a trade-off
between phase noise performance and power-up time.
This depends on the number of gain changes the AGC loop needs to cycle through
and AGC settings programmed. This is described in more detail in the AGC Information
section.
This is the time for the clock and data recovery circuit to settle. This typically requires
5-bit transitions to acquire sync and is usually covered by the preamble.
Number of bits in payload by the bit period.
Signal to
Monitor
CLKOUT
MUXOUT
CVCO pin
Analog RSSI
on TEST_A pin
Rev. A | Page 25 of 44
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