ADF7025
REGISTERS
REGISTER 0—N REGISTER
MUXOUT
8-BIT INTEGER-N
15-BIT FRACTIONAL-N
ADDRESS
BITS
TRANSMIT/
TR1 RECEIVE
0
TRANSMIT
1
RECEIVE
PLE1 PLL ENABLE
0
PLL OFF
1
PLL ON
M3 M2 M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MUXOUT
REGULATOR READY (DEFAULT)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
THREE-STATE
PLL TEST MODES
Σ-∆ TEST MODES
M15 M14 M13 ...
M3 M2 M1
FRACTIONAL
DIVIDE RATIO
0
0
0
... 0
0
0
0
0
0
0
... 0
0
1
1
0
0
0
... 0
1
0
2
.
.
.
... .
.
.
.
.
.
.
... .
.
.
.
.
.
.
... .
.
.
.
1
1
1
... 1
0
0
32764
1
1
1
... 1
0
1
32765
1
1
1
... 1
1
0
32766
1
1
1
... 1
1
1
32767
N8 N7 N6 N5 N4 N3 N2 N1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
0
1
N COUNTER
DIVIDE RATIO
31
32
.
.
.
253
1
1
1
1
1
1
1
0
254
1
1
1
1
1
1
1
1
255
Figure 39. Register 0—N Register
Register 0—N Register Comments
• The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.
•
FOUT
=
XTAL
R
×
(Integer
N
+
Fractional
215
N
)
• If operating in 433 MHz band with the VCO band bit set, the desired frequency, FOUT, should be programmed to be twice the desired
operating frequency, due to removal of the divide-by-2 stage in feedback path.
Rev. A | Page 28 of 44