EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
REGISTER 3—RECEIVER CLOCK REGISTER
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
ADF7025
ADDRESS
BITS
SK8 SK7 ...
0
0
...
0
0
...
.
.
...
1
1
...
1
1
...
SK3 SK2 SK1 SEQ_CLK_DIVIDE
0011
0102
.
.
.
.
1 1 0 254
1 1 1 255
BK2
0
0
1
BK1
0
1
x
BBOS_CLK_DIVIDE
4
8
16
OK2 OK1 DEMOD_CLK_DIVIDE
004
011
102
113
FS8 FS7 ...
FS3 FS2 FS1 CDR_CLK_DIVIDE
0
0
...
0
0
1
1
0
0
...
0
1
0
2
.
.
...
.
.
.
.
1
1
...
1
1
0
254
1
1
...
1
1
1
255
Figure 42. Register 3—Receiver Clock Register
Register 3—Receiver Clock Register Comments
• Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:
BBOS_CLK =
XTAL
BBOS_CLK _ DIVIDE
• The demodulator clock (DEMOD_CLK) must be < 12 MHz, where:
DEMOD_CLK =
XTAL
DEMOD_CLK _ DIVIDE
• Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:
CDR_CLK = DEMOD_CLK
CDR_CLK _ DIVIDE
Note that this can affect the choice of XTAL, depending on the desired data rate.
• The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz.
SEQ _CLK =
XTAL
SEQ _CLK _ DIVIDE
Rev. A | Page 31 of 44
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