EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
REGISTER 4—DEMODULATOR SETUP REGISTER
DEMODULATOR LOCK SETTING
POSTDEMODULATOR BW
ADDRESS
BITS
DEMODULATOR
DS2 DS1 TYPE
0 0 LINEAR DEMODULATOR
0 1 CORRELATOR/DEMODULATOR
1 0 INVALID
1 1 INVALID
DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH
0
0 0 0 SERIAL PORT CONTROL – FREE RUNNING
1
0 0 1 SERIAL PORT CONTROL – LOCK THRESHOLD
2
0 1 0 SYNC WORD DETECT – FREE RUNNING
3
0 1 1 SYNC WORD DETECT – LOCK THRESHOLD
4
1 0 X INTERRUPT/LOCK PIN LOCKS THRESHOLD
5
1 1 DL8 DEMOD LOCKED AFTER DL8–DL1 BITS
INT/LOCK PIN
–
–
OUTPUT
OUTPUT
INPUT
–
MODE5 ONLY
DL8 DL7 ...
0 0 ...
0 0 ...
0 0 ...
.
.
...
1 1 ...
1 1 ...
DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT
0000
0011
0102
.
.
.
.
1 1 0 254
1 1 1 255
Figure 43. Register 4—Demodulator Setup Register
Register 4—Demodulator Setup Register Comments
• Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow
the ADF7025 to demodulate data-encoding schemes that have run-length constraints greater than 7.
• Post_Demod_BW = 211 × π × FCUTOFF , where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times
DEMOD_CLK
the data rate.
• For Mode 5, the Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the
Register 3—Receiver Clock Register section.
Rev. A | Page 32 of 44
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