EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
Rx
RESET
IF FILTER DIVIDER
DISCRIMINATOR BW
ADDRESS
BITS
DEMOD
RESET
CDR
RESET
RxDATA
RI1 INVERT
0 RxDATA
1 RxDATA
CA1 FILTER CAL
0 NO CAL
1 CALIBRATE
ML1 MIXER LINEARITY
0 DEFAULT
1 HIGH
DP1 DOT PRODUCT
0 CROSS PRODUCT
1 INVALID
LG1 LNA MODE
0 DEFAULT
1 REDUCED GAIN
LI2 LI1 LNA BIAS
0 0 800µA (DEFAULT)
FC9 .
0.
0.
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1.
FILTER CLOCK
FC6 FC5 FC4 FC3 FC2 FC1 DIVIDE RATIO
0000011
0000102
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1 1 1 1 1 1 511
Figure 45. Register 6—Correlator/Demodulator Register
Register 6—Correlator/Demodulator Register Comments
• See the FSK Correlator/Demodulator section for an example of how to determine register settings.
• Nonadherence to correlator programming guidelines results in poor sensitivity.
• The filter clock is used to calibrate the LP filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz.
The formula is XTAL/FILTER_CLOCK_DIVIDE.
• The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19
is set high.
• Discriminator_BW = DEMOD_CLK/(4 × DEVIATION_Frequency). See the FSK Correlator/Demodulator section.
Maximum value = 600.
• When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when
linearity is a concern. See the Readback Format section for details of the different Rx modes.
Rev. A | Page 34 of 44
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