EVAL-ADV7619EB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7619EB1Z' PDF : 24 Pages View PDF
Data Sheet
ADV7619
GENERAL DESCRIPTION
The ADV7619 is a high quality, two input, one output (2:1)
multiplexed High-Definition Multimedia Interface (HDMI®)
receiver. The ADV7619 is offered in professional (no HDCP
keys) and commercial versions. The operating temperature
range is 0°C to 70°C.
The ADV7619 incorporates a dual input HDMI-capable
receiver that supports all mandatory 3D TV formats defined in
the HDMI 1.4a specification, HDTV formats up to 1080p 36-bit
Deep Color/2160p 8-bit, and display resolutions up to 4k × 2k
(3840 × 2160 at 30 Hz). It integrates an HDMI CEC controller
that supports the capability discovery and control (CDC) feature.
The ADV7619 incorporates Xpressview™ fast switching on both
input HDMI ports. Using the Analog Devices, Inc., hardware-
based HDCP engine to minimize software overhead, Xpressview
technology allows fast switching between both HDMI input ports
in less than 1 sec.
Each HDMI port has dedicated 5 V detect and Hot Plug™ assert
pins. The HDMI receiver also includes an integrated program-
mable equalizer that ensures robust operation of the interface
with long cables.
The ADV7619 offers a flexible audio output port for audio data
extraction from the HDMI stream. HDMI audio formats, includ-
ing SACD via DSD and HBR, are supported by the ADV7619.
The HDMI receiver has advanced audio functionality, such as
a mute controller, that prevents audible extraneous noise in the
audio output.
The ADV7619 contains one main component processor (CP),
which processes video signals from the HDMI receiver up to
1080p 36-bit Deep Color. It provides features such as contrast,
brightness and saturation adjustments, STDI detection block,
free-run, and synchronization alignment controls.
For video formats with pixel clocks higher than 170 MHz, the
video signals received on the HDMI receiver are output directly
to the pixel port output. To accommodate the higher bandwidth
required for these higher resolutions, the output on the pixel bus
consists of two 24-bit buses running at up to 150 MHz: one bus
contains the even pixels, and the other bus contains the odd
pixels. When these two buses are combined, they allow the
transfer of video data with pixel clocks up to 300 MHz. In this
mode, both 4:4:4 RGB 8-bit and 4:2:2 12-bit are supported.
Fabricated in an advanced CMOS process, the ADV7619
is provided in a 14 mm × 14 mm, 128-lead, surface-mount,
RoHS-compliant TQFP_EP package and is specified over the
0°C to 70°C temperature range.
DETAILED FUNCTIONAL BLOCK DIAGRAM
XTALP
XTALN
SCL
SDA
CS
CEC
RXA_5V
RXB_5V
HPA_A/INT2*
HPA_B
DDCA_SD A
DDCA_SC L
DDCB_SD A
DDCB_SC L
RXA_C±
RXB_C±
RXA_0±
RXA_1±
RXA_2±
RXB_0±
RXB_1±
RXB_2±
DPLL
300MHz VIDEO PATH
CEC
CONTROLLER
5V DETECT
AND HDP
CONTROLLER
CONTROL
INTERFACE
I2C
CONTROL AND DATA
EDID
REPEATER
CONTROLLER
HDCP
KEYS
PLLs
HDCP
ENGINE
HDMI
PROCESSOR
DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
EQUALIZER SAMPLER
EQUALIZER SAMPLER
PACKET
PROCESSOR
BACK-END
COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
A
B
C
INTERRUPT
CONTROLLER
(INT1, INT2)
PACKET/
INFOFRAME
MEMORY
MUTE
AUDIO
PROCESSOR
ADV7619
*INT2 CAN BE MADE AVAILABLE ON ONE OF THESE PINS: HPA_A/INT2, MCLK/INT2, OR SCLK/INT2.
Figure 2.
P0 TO P11
P12 TO P23
P24 TO P35
P36 TO P47
LLC
HS
VS/FIELD/ALSB
DE
INT1
INT2*
AP1
AP2
AP3
AP4
AP5
SCLK/INT2*
MCLK/INT2*
AP0
Rev. B | Page 3 of 24
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