ADV7619
Data Sheet
DATA AND I2C TIMING CHARACTERISTICS
Table 3.
Parameter
CLOCK AND CRYSTAL
Crystal Frequency, XTAL
Crystal Frequency Stability
LLC Frequency Range
I2C PORTS
SCL Frequency
SCL Minimum Pulse Width High1
SCL Minimum Pulse Width Low1
Start Condition Hold Time1
Start Condition Setup Time1
SDA Setup Time1
SCL and SDA Rise Time1
SCL and SDA Fall Time1
Stop Condition Setup Time1
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark-Space Ratio1
DATA AND CONTROL OUTPUTS1, 2
Data Output Transition Time
I2S PORT, MASTER MODE1
SCLK Mark-Space Ratio
LRCLK Data Transition Time
I2Sx Data Transition Time
Symbol Test Conditions/Comments
Min
13.5
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
t11
t12
t15:t16
t17
t18
t19
t20
600
1.3
600
600
100
0.6
5
45:55
End of valid data to negative LLC edge
Negative LLC edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
45:55
1 Data guaranteed by characterization.
2 DLL bypassed on clock path.
Typ
Max
28.63636
±50
170
400
300
300
55:45
1.0
0.1
55:45
10
10
5
5
Unit
MHz
ppm
MHz
kHz
ns
μs
ns
ns
ns
ns
ns
μs
ms
% duty cycle
ns
ns
% duty cycle
ns
ns
ns
ns
Timing Diagrams
t3
SDA
t5
t3
t6
t1
SCL
t2
t7
t4
t8
Figure 3. I2C Timing
Rev. B | Page 6 of 24