Data Sheet
t9
t10
LLC
P0 TO P47, HS,
VS/FIELD/ALSB, DE
t11
t12
Figure 4. Pixel Port and Control SDR Output Timing
SCLK
LRCLK
I2Sx
LEFT-JUSTIFIED
MODE
I2Sx
I2S MODE
I2Sx
RIGHT-JUSTIFIED
MODE
t15
t16
t17
t18
t19
MSB
MSB – 1
t20
t19
MSB
MSB – 1
t20
MSB
NOTES
1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN.
2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE
ON THE FOLLOWING PINS: AP1, AP2, AP3, AND AP4.
Figure 5. I2S Timing
t19
t20
LSB
ADV7619
Rev. B | Page 7 of 24