EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 28 Pages View PDF
AD7691
Data Sheet
THEORY OF OPERATION
IN+
REF
GND
MSB
SWITCHES CONTROL
LSB SW+
131,072C 65,536C
4C
2C
C
C
131,072C 65,536C
4C
2C
C
C
COMP
CONTROL
LOGIC
BUSY
OUTPUT CODE
MSB
LSB SW–
CNV
IN–
Figure 27. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7691 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.
The part is capable of converting 250,000 samples per second
(250 kSPS) and powers down between conversions. When
operating at 1 kSPS, for example, it consumes 50 µW typically,
which is ideal for battery-powered applications.
The AD7691 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7691 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7691 is shown in
Figure 28 and Table 9.
The AD7691 is specified from 2.3 V to 5.25 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead LFCSP that combines space
savings and allows flexible configurations.
011...111
011...110
011...101
The part is pin-for-pin compatible with the 18-bit AD7690 as
well as the 16-bit AD7687 and AD7688.
CONVERTER OPERATION
The AD7691 is a successive approximation ADC based on a
charge redistribution DAC. Figure 27 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
100...010
100...001
100...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
connected to the two comparator inputs.
–FSR + 0.5LSB
+FSR – 1.5LSB
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
ANALOG INPUT
Figure 28. ADC Ideal Transfer Function
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
Table 9. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output
Code (Hex)
FSR − 1 LSB
+4.999962 V
0x1FFFF1
Midscale + 1 LSB
+38.15 µV
0x00001
Midscale
0V
0x00000
Midscale − 1 LSB
−38.15 µV
0x3FFFF
−FSR + 1 LSB
−4.999962 V
0x20001
−FSR
−5 V
0x200002
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144).
Rev. E | Page 14 of 28
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