EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 28 Pages View PDF
Data Sheet
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7691 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and VDD. To reduce the
supplies needed, the VIO and VDD pins can be tied together. The
AD7691 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
The AD7691 powers down automatically at the end of each
conversion phase, and therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.
1000
10
VDD = 5V
VIO
0.1
0.001
10
100
1k
10k
100k
1M
SAMPLING RATE (SPS)
Figure 33. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR431, ADR433, ADR434, and ADR435.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 34.
AD7691
5V 10kΩ
1µF
5V
5V
10Ω
AD8031 10µF
1µF
1
REF
VDD
VIO
AD7691
1OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 34. Example of an Application Circuit
DIGITAL INTERFACE
Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7691 is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, the Blackfin® processors or
the high performance, mixed-signal DSP family. In this mode,
the AD7691 can use either a 3-wire or 4-wire interface. A 3-
wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections and is useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high, and the chain mode is selected if SDI is
low. The SDI hold time is such that when SDI and CNV are
connected together, the chain mode is selected.
The initial state of SDO on power up is indeterminate.
Therefore, in order to put SDO in a known state, a conversion
must be initiated and all data bits clocked out.
In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 38 and Figure 42).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 46).
Rev. E | Page 17 of 28
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