EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 28 Pages View PDF
Data Sheet
AD7691
TYPICAL CONNECTION DIAGRAM
Figure 29 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available.
V+
REF1
10µF2
5V
100nF
V+
0 TO VREF
ADA4841-2 3 V–
V+
VREF TO 0
ADA4841-2 3 V–
15Ω
2.7nF
4
15Ω
2.7nF
4
REF
IN+
VDD
AD7691
IN–
GND
VIO
SDI
SCK
SDO
CNV
100nF
1.8V TO VDD
3- OR 4-WIRE INTERFACE5
1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2 CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3 SEE TABLE 9 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 29. Typical Application Diagram with Multiple Supplies
ANALOG INPUTS
Figure 30 shows an equivalent circuit of the input structure of
the AD7691.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur if the input buffer (U1)
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
VDD
IN+
OR IN–
GND
D1
CPIN
D2
RIN
CIN
Figure 30. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 3 kΩ and is a lumped component composed of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits noise.
When the source impedance of the driving circuit is low, the
AD7691 can be driven directly. Large source impedances
significantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to
the input impedance. The maximum source impedance
depends on the amount of THD that can be tolerated.
The THD degrades as a function of the source impedance and
the maximum input frequency as shown in Figure 31.
–80
VREF = VDD 5V
–85
–90
–95
–100
–105
–110
–115
250Ω
100Ω
33Ω
50Ω 15Ω
–120
–125
–130
0
10 20 30 40 50 60 70 80 90
FREQUENCY (kHz)
Figure 31. THD vs. Analog Input Frequency and Source Resistance
Rev. E | Page 15 of 28
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