EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 28 Pages View PDF
AD7691
Data Sheet
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35, and the corresponding timing is given in
Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers, but CNV must be returned high before
the minimum conversion time elapses and then held high for
the maximum possible conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7691 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge can allow a faster reading rate, provided it has
an acceptable hold time. After the 18th SCK falling edge, or
when CNV goes high, whichever occurs first, SDO returns to
high impedance.
CNV
VIO
SDI AD7691 SDO
SCK
CONVERT
DIGITAL HOST
DATA IN
CLK
Figure 35. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCNVH
CNV
tCYC
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCKL
tSCK
SCK
1
2
3
16
17
18
tHSDO
tSCKH
tEN
tDSDO
tDIS
SDO
D17
D16
D15
D1
D0
Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. E | Page 18 of 28
Share Link: 
