FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:
1. “Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3 are
unaffected and retain their previous value.
2. “Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e. all conventional mode.
WGATE
0
0
1
1
GAP
0
1
0
1
Table 45 - Affects of WGATE and GAP Bits
LENGTH OF GAP2 PORTION OF GAP 2 WRITTEN BY
MODE
FORMAT FIELD
WRITE DATA OPERATION
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
22 Bytes
22 Bytes
22 Bytes
41 Bytes
0 Bytes
19 Bytes
0 Bytes
38 Bytes
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the FIFO
the LOCK Command has been added. This command should only be used by the FDC routines, and application
software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE
command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE
command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic “1” all subsequent
“software RESETS by the DOR and DSR registers will not change the previously set parameters to their default
values. All “hardware” RESET from the RESET pin will set the LOCK bit to logic “0” and return the EFIFO,
FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK
command. This byte reflects the value of the LOCK bit set by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE
command the eighth byte of the DUMPREG command has been modified to contain the additional data from these
two commands.
COMPATIBILITY
The FDC37N869 was designed with software compatibility in mind. It is a fully backwards-compatible solution
with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility
with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC,
all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode,
depending on how the IDENT and MFM bits are configured by the system BIOS.
Parallel Port Floppy Disk Controller
In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected,
the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be
selected in Configuration Register 4. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on
the parallel port pins.
PPFD1: Drive 0 is on the FDC pins
Drive 1 is on the Parallel port pins
PPFD2: Drive 0 is on the Parallel port pins
Drive 1 is on the Parallel port pins
When the PPFDC is selected the following pins are set as follows:
1. nDACK: Assigned to the parallel port device during configuration.
2. PDRQ (assigned to the parallel port): not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z
SMSC DS – FDC37N869
Page 57
Rev. 11/09/2000
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