FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
Note1: The Parallel Port Control register reads as “Cable Not Connected” when the PP FDC is enabled; i.e.,
STROBE = AUTOFD = SLC = 0 and nINIT = 1
SERIAL PORT (UART)
The FDC37N869 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE
registers and the NS16550A. The UARTs perform serial-to-parallel conversion on received characters and
parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 115.2K
baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is
capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of
supporting the MIDI data rate. Refer to the FDC37N869 Configuration Registers for information on disabling,
powering down and changing the base address of the UARTs. The interrupt from a UART is enabled by
programming OUT2 of that UART to a logic “1”. When OUT2 is a logic “0” the UART Interrupt is disabled.
Register Description
Addressing of the accessible registers of the Serial Port is shown below (Table 48). The base addresses of the
serial ports are defined by the configuration registers (see section CONFIGURATION on page 101. The Serial Port
registers are located at sequentially increasing addresses above these base addresses. The FDC37N869
contains two serial ports, each of which contain a register set as described below.
DLAB1
Table 48 - Addressing the Serial Port
A2
A1
A0
REGISTER NAME
0
0
0
0 Receive Buffer (read)
0
0
0
0 Transmit Buffer (write)
0
0
0
1 Interrupt Enable (read/write)
X
0
1
0 Interrupt Identification (read)
X
0
1
0 FIFO Control (write)
X
0
1
1 Line Control (read/write)
X
1
0
0 Modem Control (read/write)
X
1
0
1 Line Status (read/write)
X
1
1
0 Modem Status (read/write)
X
1
1
1 Scratchpad (read/write)
1
0
0
0 Divisor LSB (read/write)
1
0
0
1
Note1: DLAB is Bit 7 of the Line Control Register
Divisor MSB (read/write)
RECEIVE BUFFER REGISTER (RB)
The Receive Buffer register (Address Offset = 0H, DLAB = 0, READ ONLY) holds the received incoming data byte.
Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses
an additional shift register to receive the serial data stream and convert it to a parallel 8 bit character which is
transferred to the Receive Buffer register. The shift register is not accessible.
TRANSMIT BUFFER REGISTER (TB)
The Transmit Buffer register (Address Offset = 0H, DLAB = 0, WRITE ONLY) contains the data byte to be
transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert
the 8 bit data character to a serial format. This shift register is loaded from the Transmit Buffer when the
transmission of the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
The lower four bits of the Interrupt Enable register (Address Offset = 1H, DLAB = 0, READ/WRITE) control the
enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system
by resetting bits 0 through 3 of this register. Similarly, by setting the appropriate bits of this register to a high
selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and
SMSC DS – FDC37N869
Page 59
Rev. 11/09/2000
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