FDC37N869 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

FDC37N869

5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications

SMSC -> Microchip 

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disables any Serial Port interrupt out of the FDC37N869. All other system functions operate in their normal

manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are

described below.

ERDAI, Bit 0

The ERDAI bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when set

to logic “1”.

ETHREI, Bit 1

The ETHREI bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.

ELSI, Bit 2

The ELSI bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the

interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.

EMSI, Bit 3

The EMSI bit enables the MODEM Status Interrupt when set to logic “1”. An MSI is caused when one of the Modem

Status Register bits changes state.

Reserved, Bits 4 - 7

Bits 4 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.

INTERRUPT IDENTIFICATION REGISTER (IIR)

By accessing the Interrupt Identification register (Address Offset = 2H, DLAB = X, READ), the host CPU can

determine the highest priority interrupt and its source. Four levels of interrupt priority exist. They are in descending

order of priority:

1. Receiver Line Status (highest priority)

2. Received Data Ready

3. Transmitter Holding Register Empty

4. MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt

Identification Register (refer to the Interrupt Control Table,

Table 49). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority

pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current

indication does not change until access is completed.

Interrupt Pending, Bit 0

The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an

interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a

pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.

Interrupt ID, Bits 1 - 2

The Interrupt ID bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt

Control Table (

Table 49).

Time-Out, Bit 3

In non-FIFO mode, the Time-Out bit is a logic “0”. In FIFO mode the Time-Out bit is set along with bit 2 when a

time-out interrupt is pending.

SMSC DS – FDC37N869

Page 60

Rev. 11/09/2000

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