GL640USB-A View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL640USB-A' PDF : 39 Pages View PDF
GL640USB, GL640USB-A
instruction using the INDF register actually accesses the register pointed by the INDAR register.
TIMER (Address 01h, Timer register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIMER7 TIMER6 TIMER5 TIMER4 TIMER3 TIMER2 TIMER1 TIMER0
After timer is enable, the timer will start to count up. The Timer Interrupt is generated when the
TIMER register overflows from FFh to 00h.
Value on POR: “0 0 0 0 0 0 0 0”
PCL (Address 02h/82h, Program Counter’s low byte)
R/W
R/W
R/W
R/W
R/W
PCL7 PCL6 PCL5 PCL4 PCL3
R/W
PCL2
R/W
PCL1
R/W
PCL0
The Program Counter (PC) is 11-bit wide. The low byte comes from the PCL register, which is a
readable and writable register. The high byte is not directly readable or writable and comes from
PCHBUF. The GL600USB has a 4 level deep x 11-bit wide hardware stake. The stake space is
not part of either program or data space and the stack pointer is not readable or writable. The PC
is pushed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The
stack is poped in the event of a RETIA, RETI or a RET instruction execution. PCHBUF is not
affected by a push or pop operation.
Value on POR: “0 0 0 0 0 0 0 0”
Status (Address 03h, Status register)
R/W
R/W
R/W
R/W
BS
ZO
HC
CA
BS: Bank Select
1: Bank 1 (80h-FFh)
0: Bank 0 (00h-7Fh)
ZO: Zero bit
1: The result of an arithmetic or logic operation is zero
0: The result of an arithmetic or logic operation is not zero
HC: Half Carry/Borrow bit
1: A carry-out from the 4th low order bit
Revision 1.1
-12-
Jun. 7, 1999
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