GL640USB-A View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL640USB-A' PDF : 39 Pages View PDF
INTFLG
UINTEN
USBFLG
CTLDAT/
STSDAT
CTLLEN/
STSLEN
FFCFG
FFCTL
FF0DAT
FF1DAT
LINE_L
LINE_H
EPPCTL
EPPAD
GL640USB, GL640USB-A
93 interrupt flag
94 USB interrupt enable
95 USB interrupt flag
96 Control/status data buffer
97 Control/status data length
98 FIFO configuration register
99 FIFO control
9A data port for FIFO0
9B data port for FIFO1
9C Read : max. length of TX data packet
Write : line size (low byte)
9D Read : received data length /
Write : line size (high byte)
9E EPP control / status
9F EPP interface AD0-7
IODEVCTL (offset 90h)
R/W
R/O
R/O
R/O
R/W
R/W
R/W
EXTCLK NC
NC
GPI4
CKSEL2 CKSEL1 CKSEL0
EN
CLKTYP - select crystal frequency, this bit reflects the OSCSEL pin
0 - 12MHz, 1 - 48MHz
CKSEL[2:0] - select CLKOUT frequency, default=8MHz
000 - stop CLKOUT
100 - 8MHz
001 - 24MHz
101 - 6MHz
010 - 16MHz
110 - 12KHz
011 - 12MHz
GPI4
- this bit reflects the status of GPI4 input pad
EXTCLKEN -
Enable EXTCLK output
0 – set EXTCLK to tri-state
1- enable EXTCLK
ENDPCTL(offset 91h)
R/O
CLKTYP
Revision 1.1
-16-
Jun. 7, 1999
Share Link: 
