GL640USB-A View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL640USB-A' PDF : 39 Pages View PDF
GL640USB, GL640USB-A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Read this register will pop data from FIFO0. Write this register will push data into FIFO0.
FF1DAT ( offset 9Bh )
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Read this register will pop data from FIFO1. Write this register will push data into FIFO1.
MAXLEN/LINE_L ( offset 9Ch )
R/W
R/W
R/W
R/W
R/W
R/W
LINE7 LINE6 LINE5 LINE4 LINE3 LINE2
Read:
MAXLEN - Equal to 64
Write:
LINE_L
- The low byte of EPP accessing length
R/W
LINE1
R/W
LINE0
DATLEN / LINE_H ( offset 9Dh )
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9
Read:
DATLEN
- The length of data received by the RX endpoint
Write:
LINE_H
- The high byte of EPP accessing length
R/W
LINE8
EPPCTL ( offset 9Eh )
R/W
R/W
R/W
R/W
R/W
R/W
R/O
GLTHFLT WRCHK
ACTIVE
A2CHK
A1CHK
A0CHK
INT_
This register is available only in EPP mode.
ADOE
- Set this bit to ‘1’ can drive data in EPPAD register to
pins D7-0
INT_
- This bit reflects the status of INT_ pin.
R/W
ADOE
Revision 1.1
-20-
Jun. 7, 1999
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