GL640USB-A View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL640USB-A' PDF : 39 Pages View PDF
GL640USB, GL640USB-A
RXCTL0 ( offset 13h )
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
RXDIS RXSETUP RXOUT RXSEQ RXCNT3 RXCNT2 RXCNT1 RXCNT0
Default=8’h0e
This register is used to check the received data byte count, data toggle, and transaction token on endpoint
0. When the EP0RX interrupt is detected, firmware should first check this register to decide the received
data is valid or not. At this time, RXDIS bit is set by hardware to prevent the current data in endp0 FIFO
overwritten by next incoming data. After extracting data from endp0 FIFO, firmware should clear RXDIS to
enable receiving capability on endp0.
RXCNT[3:0]
RXSEQ
RXOUT
RXSETUP -
RXDIS
- Received data byte count.
- 1 - The received data is DATA1
0 - The received data is DATA0
- 1 - The received token is OUT.
1 - The received token is SETUP.
- Disable receiving capability on endpoint 0
Upon successfully receiving a data packet on endpoint 0, hardware will
automatically set this bit to ‘1’. At this time, no more SETUP/OUT data on
endpoint 0 can be accepted, hardware will respond with NAK.
0 - Endp0 FIFO is available for data receiving.
1 – Endp0 FIFO is not available
Note: Firmware must take care the data toggle check and decide if current RX data is valid.
TXCTL0 ( offset 14h )
R/W
R/W
R/W
R/W
R/W
R/W
TXOE TXSEQ TXCNT3 TXCNT2 TXCNT1 TXCNT0
Default=8’h00
This register is used to control the data byte count, data toggle of the transmitted data on endpoint 0. If
there is data to be sent to endpoint 0, firmware should first push data into FFDAT0 register, and then set the
pushed byte count to TXCNT3-0, set the data toggle to TXSEQ, and finally turn on TXOE to enable the data
transmission.
Revision 1.1
-24-
Jun. 7, 1999
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