HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their associated
control register PAC, PBC, etc play a prominent role. These registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory table. The data I/O registers, are used to transfer
the appropriate output or input data on the port. The control registers specifies which pins of the port are
set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control
register must be set high, for an output it must be set low. During program initialisation, it is important to
first setup the control registers to specify which pins are outputs and which are inputs before reading data
from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly
program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during
normal program operation is a useful feature of these devices.
System Control Registers - CTRL0, CTRL1, CTRL2
These registers are used to provide control over several internal functions. These functions include the
external Interrupt edge trigger type, the PWM function control, Time Base period selection and LXT
oscillator low power control,etc.
· CTRL0 Register - HT48R064G
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
PFDC
LXTLP CLKMOD
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
0
0
0
· CTRL0 Register - HT48R065G
Bit
7
6
5
4
Name
¾
PFDCS
¾
¾
R/W
¾
R/W
¾
¾
POR
¾
0
¾
¾
3
2
1
0
¾
PFDC
LXTLP CLKMOD
¾
R/W
R/W
R/W
¾
0
0
0
Bit
Name
R/W
POR
· CTRL0 Register - HT48R0662G
7
6
5
4
3
2
1
0
¾
PFDCS PWMSEL PWMC1 PWMC0 PFDC
LXTLP CLKMOD
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
¾
0
0
0
0
0
0
0
unimplemented, read as ²0²
PFDCS: PFD clock source selection
0: timer0
1: timer1
For HT48R064G device, this bit is read as 0 and the PFD clock source always comes from the
timer.
PWMSEL: PWM type selection
0: 6+2 type
1: 7+1 type
PWMC1: I/O or PWM1 selection
0: I/O
1: PWM1
PWMC0: I/O or PWM0 selection
0: I/O or other pin-shared functions
1: PWM0
Rev. 1.10
34
October 23, 2012
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