HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
· CTRL1 Register
Bit
Name
R/W
POR
7
INTEG1
R/W
1
6
INTEG0
R/W
0
5
TBSEL1
R/W
0
4
TBSEL0
R/W
0
3
WDTEN3
R/W
1
2
WDTEN2
R/W
0
1
WDTEN1
R/W
1
0
WDTEN0
R/W
0
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210/fTP
01: 211/fTP
10: 2121/fTP
11: 2131/fTP
Bit 3~0
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT function disabled
Other values: WDT function enabled - Recommended value is 0101
If the ²watchdog timer enable configuration option² is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
Note: The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0 is set to 1010. The WDT is enabled when either the WDT configuration option is enabled
or when bits WDTEN3~WDTEN0¹1010.
· CTRL2 Register - HT48R0662G
Bit
7
6
5
4
3
2
1
0
Name PCFG1 PCFG0
¾
¾
¾
¾
¾
LXTEN
R/W
R/W
R/W
¾
¾
¾
¾
¾
R/W
POR
0
0
¾
¾
¾
¾
¾
1
Bit 7~6
Bit 5~1
Bit 0
PCFG1, PCFG0: Pin configuration
00: PFD/TC0/INT/TC1 pin-shared with PA1/PA2/PA3/PA4
01: PFD/TC0/INT/TC1 pin-shared with PC5/PC4/PC3/PC2
10: PFD/TC0/INT/TC1 pin-shared with PB0/PB1/PB2/PB3
11: PFD/TC0/INT/TC1 pin-shared with PE0/PE1/PE2/PE3
Unimplemented, read as ²0²
LXTEN: LXT Oscillator on/off control after execution of HALT instruction
0: LXT oscillator off after HALT instruction
1: LXT oscillator on after HALT instruction
Rev. 1.10
36
October 23, 2012
Share Link: 
