HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Interrupt Operation
A Timer/Event Counter overflow, an active edge on the external interrupt pin, a comparator output
transition, an OPA output falling edge or a Time Base event will all generate an interrupt request by
setting their corresponding request flag. When this happens, the Program Counter, which stores the
address of the next instruction to be executed, will be transferred onto the stack. The Program Counter
will then be loaded with a new address which will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this
vector will usually be a JMP statement which will jump to another section of program which is known
as the interrupt service routine. Here is located the code to control the appropriate interrupt. The
interrupt service routine must be terminated with a RETI instruction, which retrieves the original
Program Counter address from the stack and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be
cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although the interrupt will not be immediately serviced,
the request flag will still be recorded. If an interrupt requires immediate servicing while the program is
already in another interrupt service routine, the EMI bit should be set after entering the routine, to
allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the
interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request then
it will take 3 cycles before the program jumps to the interrupt vector.
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked by
resetting the EMI bit.
HT48R064G
Interrupt Source
Priority
External Interrupt
1
Timer/Event Counter 0 Overflow
2
Time Base Overflow
3
Multi-function interrupt
(Comparator, OPA0, OPA1)
4
Vector
04H
08H
14H
18H
HT48R065G/HT48R066G/HT48R0662G
Interrupt Source
Priority
External Interrupt
1
Timer/Event Counter 0 Overflow
2
Timer/Event Counter 1 Overflow
3
Time Base Overflow
4
Multi-function interrupt
(Comparator, OPA0, OPA1)
5
Vector
04H
08H
0CH
14H
18H
Rev. 1.10
87
October 23, 2012
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