HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
In cases where both external and internal interrupts are enabled and where an external and internal in-
terrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit,
INTE, must first be set. An actual external interrupt will take place when the external interrupt request
flag, INTF, is set, a situation that will occur when an edge transition appears on the external INT line.
The type of transition that will trigger an external interrupt, whether high to low, low to high or both is
determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in the CTRL1
control register. These two bits can also disable the external interrupt function.
INTEG1
0
0
1
1
INTEG0
0
1
0
1
Edge Trigger Type
External interrupt disable
Rising edge Trigger
Falling edge Trigger
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an exter-
nal interrupt pin if the corresponding external interrupt enable bit in the INTC register has been set
and the edge trigger type has been selected using the CTRL1 register. The pin must also be setup as
an input by setting the corresponding PAC.3 bit in the port control register. When the interrupt is en-
abled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine
call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced,
the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automati-
cally cleared to disable other interrupts. Note that any pull-high resistor connections on this pin will
remain valid even if the pin is used as an external interrupt input.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt
vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Time Base Interrupt
For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt
enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base
request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is
enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will
take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset
and the EMI bit will be automatically cleared to disable other interrupts.
Rev. 1.10
88
October 23, 2012
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