HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
Operating Modes and System Clocks
Present day applications require that their
microcontrollers have high performance but often still
demand that they consume as little power as possible,
conflicting requirements that are especially true in bat-
tery powered portable applications. The fast clocks re-
quired for high performance will by their nature increase
current consumption and of course vice-versa, lower
speed clocks reduce current consumption. As Holtek
has provided these devices with both high and low
speed clock sources and the means to switch between
them dynamically, the user can optimise the operation of
their microcontroller to achieve the best perfor-
mance/power ratio.
System Clocks
The device has many different clock sources for both
the CPU and peripheral function operation. By providing
the user with a wide range of clock options using config-
uration options and register programming, a clock sys-
tem can be configured to obtain maximum application
performance.
H ig h S p e e d
O s c illa tio n
The main system clock, can come from either a high fre-
quency, fH, or low frequency, fL, source, and is selected
using the HLCLK bit and CKS2~CKS0 bits in the SMOD
register. The high speed system clock can be sourced
from either an HXT or HIRC oscillator, selected via a
configuration option. The low speed system clock
source can be sourced from internal clock fL. The other
choice, which is a divided version of the high speed sys-
tem oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the periph-
eral circuits, the substitute clock, fSUB, and the Time
Base clock, fTBC. Each of these internal clocks are
sourced by the LIRC oscillators. The fSUB clock is used
to provide a substitute clock for the microcontroller just
after a wake-up has occurred to enable faster wake-up
times.
HXT
fH
6 - s ta g e P r e s c a le r
H IR C
fH /2
fH /4
H ig h S p e e d O s c illa tio n
fH /8
C o n fig u r a tio n O p tio n
fH /1 6
fH /3 2
fH /6 4
fL
fS Y S
L IR C
Low S peed
O s c illa tio n
H LC LK ,
C K S 2 ~ C K S 0 b its
fS U B
F a s t W a k e -u p fro m S L E E P M o d e o r
ID L E M o d e C o n tr o l ( fo r H X T o n ly )
fS U B
fS Y S /4
fS
W DT
fS C o n fig u r a tio n O p tio n
fT B C
fT B
fS Y S /4
T im e B a s e
TBC K
System Clock Configurations
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the
power. Thus there is no fH~fH/64 for peripheral circuit to use.
Rev. 1.40
32
November 22, 2016
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