HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
The maximum time out period is when the 218 division ra-
tio is selected. As an example, with a 32 kHz LIRC oscil-
lator as its source clock, this will give a maximum
watchdog period of around 8 second for the 218 division
ratio, and a minimum timeout of 7.8ms for the 28 division
ration.
· WDTC Register
Bit
Name
R/W
POR
7
WE4
R/W
0
6
WE3
R/W
1
5
WE2
R/W
0
4
WE1
R/W
1
3
WE0
R/W
0
2
WS2
R/W
0
1
WS1
R/W
1
0
WS0
R/W
1
Bit 7~3
WE4~WE0: WDT function software control
If the WDT configuration option is ²always enable²:
10101 or 01010: Enabled
Other: Reset MCU
If the WDT configuration option is ²controlled by the WDT control register²:
10101: Disabled
01010: Enabled
Other: Reset MCU
When these bits are changed by the environmental noise or software setting to reset the
microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit
in the CTRL register will be set to 1.
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28/fS
001: 210/fS
010: 212/fS
011: 214/fS
100: 215/fS
101: 216/fS
110: 217/fS
111: 218/fS
· CTRL Register
Bit
Name
R/W
POR
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
7
6
5
4
3
2
1
0
FSYSON
¾
¾
¾
¾
LVRF
LRF
WRF
R/W
¾
¾
¾
¾
R/W
R/W
R/W
0
¾
¾
¾
¾
x
0
0
²x² unknown
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Unimplemented, read as ²0²
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can
only be cleared to 0 by the application program.
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values.
This in effect acts like a software reset function. This bit can only be cleared to 0 by the
application program.
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.
Rev. 1.40
41
November 22, 2016
Share Link: 
