HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
range between 0.9V~VLVR must exist for a time
greater than that specified by tLVR in the A.C. charac-
teristics. If the low supply voltage state does not ex-
ceed this value, the LVR will ignore the low supply
voltage and will not perform a reset function. The ac-
tual VLVR value can be selected by the LVS bits in the
LVRC register. If the LVS7~LVS0 bits are changed to
some certain values by the environmental noise or
software setting, the LVR will reset the device after
2~3 LIRC clock cycles. When this happens, the LRF
bit in the CTRL register will be set to 1. After power on
the register will have the value of 01010101B.
Note that the LVR function will be automatically dis-
abled when the device enters the power down mode.
LV R
tR S T D + tS S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=16.7ms
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal opera-
tion is the same as LVR reset except that the Watch-
dog time-out flag TO will be set to ²1².
W D T T im e - o u t
In te rn a l R e s e t
tR S T D + tS S T
Note: tRSTD is power-on delay, typical time=50ms
WDT Time-out Reset during Normal Operation
Timing Chart
· Watchdog Time-out Reset during SLEEP or IDLE
Mode
The Watchdog time-out Reset during SLEEP or IDLE
Mode is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the
Program Counter and the Stack Pointer will be
cleared to ²0² and the TO flag will be set to ²1². Refer
to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS S T
In te rn a l R e s e t
WDT Time-out Reset during SLEEP or IDLE
Timing Chart
Note:
The tSST is 15~16 clock cycles if the system clock
source is provided by HIRC. The tSST is 128 clock
for HXT. The tSST is 1~2 clock for LIRC.
Reset Initial Conditions
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
SLEEP or IDLE Mode function or Watchdog Timer. The
reset flags are shown in the table:
TO PDF
RESET Conditions
0 0 Power-on reset
u
u
RES or LVR reset during NORMAL or
SLOW Mode operation
1
u
WDT time-out reset during NORMAL or
SLOW Mode operation
1
1
WDT time-out reset during IDLE or
SLEEP Mode operation
Note: ²u² stands for unchanged.
The following table indicates the way in which the vari-
ous components of the microcontroller are affected after
a power-on reset occurs.
Item
Condition After RESET
Program Counter Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer Modules Timer Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs,
and AN0~AN3 as A/D input pins
Stack Pointer
Stack Pointer will point to the top
of the stack
Rev. 1.40
43
November 22, 2016
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