HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin
fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is
provided with an I/O structure to meet the needs of a wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA and PB. These I/O ports are mapped to
the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O
ports can be used for input and output operations. For input operation, these ports are non-latching, which means the
inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
· I/O Register List
Register
Name
PA
PAC
PAPU
PAWU
PB
PBC
PBPU
PRM
7
D7
D7
D7
D7
¾
¾
¾
PRML3
6
D6
D6
D6
D6
¾
¾
¾
PRML2
5
D5
D5
D5
D5
D5
D5
D5
PRML1
Bit
4
3
D4
D3
D4
D3
D4
D3
D4
D3
D4
D3
D4
D3
D4
D3
PRML0 PRMS3
2
D2
D2
D2
D2
D2
D2
D2
PRMS2
1
D1
D1
D1
D1
D1
D1
D1
PRMS1
0
D0
D0
D0
D0
D0
D0
D0
PRMS0
Pull-High Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re-
sistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of
being connected to an internal pull-high resistor. These pull-high resistors are selected using the register PAPU and
PBPU, and are implemented using weak PMOS transistors.
· PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
I/O Port A bit 7 ~ bit 0 Pull-high control
0: disable
1: enable
· PBPU Register
Bit
7
Name
¾
R/W
¾
POR
¾
6
5
4
3
2
1
0
¾
D5
D4
D3
D2
D1
D0
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
0
0
0
0
0
0
Bit 7~6
Bit 5~0
²¾² Unimplemented, read as 0
I/O Port B bit 5 ~ bit 0 Pull-high control
0: disable
1: enable
Rev. 1.40
46
November 22, 2016
Share Link: 
