HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the in-
ternal clock, fS, which is in turn supplied by the LIRC os-
cillator. The LIRC internal oscillator has an approximate
period of 32 kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period
can vary with VDD, temperature and process variations.
The Watchdog Timer source clock is then subdivided by
a ratio of 28 to 218 to give longer timeouts, the actual
value being chosen using the WS2~WS0 bits in the
WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout
period as well as the enable/disable operation. This reg-
ister together with several configuration options control
the overall operation of the Watchdog Timer.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device re-
set when its timer overflows. This means that in the ap-
plication program and during normal operation the user
has to strategically clear the Watchdog Timer before it
overflows to prevent the Watchdog Timer from execut-
ing a reset. This is done using the clear watchdog in-
structions. If the program malfunctions for whatever
reason, jumps to an unknown location, or enters an end-
less loop, these clear instructions will not be executed in
the correct manner, in which case the Watchdog Timer
will overflow and reset the device. Some of the Watch-
dog Timer options, such as always on select and clear
instruction type are selected using configuration op-
tions. With regard to the Watchdog Timer enable/dis-
able function, there are also five bits, WE4~WE0, in the
WDTC register to offer additional enable/disable and re-
set control of the Watchdog Timer. If the WDT configura-
tion option is determined that the WDT function is
always enabled, the WE4~WE0 bits still have effects on
the WDT function. When the WE4~WE0 bits value is
equal to 01010B or 10101B, the WDT function is en-
abled. However, if the WE4~WE0 bits are changed to
any other values except 01010B and 10101B, which is
caused by the environmental noise or software setting,
it will reset the microcontroller after 2~3 LIRC clock cy-
cles. If the WDT configuration option is determined that
the WDT function is controlled by the WDT control regis-
ter, the WE4~WE0 values can determine which mode
the WDT operates in. The WDT function will be disabled
when the WE4~WE0 bits are set to a value of 10101B.
The WDT function will be enabled if the WE4~WE0 bits
value is equal to 01010B. If the WE4~WE0 bits are set
to any other values by the environmental noise or soft-
ware setting, except 01010B and 10101B, it will reset
the device after 2~3 LIRC clock cycles. After power on
these bits will have the value of 01010B.
Watchdog Timer Enable/Disable Control
WDT Configura-
tion Option
WE4~WE0 Bits
WDT
Function
01010B or 10101B Enable
Always Enable
Any other value Reset MCU
Controlled by WDT
Control Register
10101B
01010B
Any other value
Disable
Enable
Reset MCU
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status
bit TO. However, if the system is in the SLEEP or IDLE
Mode, when a Watchdog Timer time-out occurs, the TO
bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods
can be adopted to clear the contents of the Watchdog
Timer. The first is a WDT reset, which means a certain
value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog
Timer software clear instructions and the third is via a
HALT instruction.
There is only one method of using software instruction
to clear the Watchdog Timer. That is to use the single
²CLR WDT² instruction to clear the WDT.
W D T C R e g is te r
W E 4 ~ W E 0 b its
R esetM C U
C LR
C LR W D T
L IR C
f L IR C
fS
fS /2 8
8 - s ta g e D iv id e r
W D T P r e s c a le r
W S 2~W S 0
(fS /2 8 ~ fS /2 18)
Watchdog Timer
8 -to -1 M U X
W D T T im e - o u t
(2 8 /fS ~ 2 18/fS )
Rev. 1.40
40
November 22, 2016
Share Link: 
