Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
APPLICATION EXAMPLE 2: 27MHZ TO 74.175MHZ
VCXO PLL Loop Characteristics with this configuration:
- Bandwidth (-3dB) = 100 Hz
- Damping Factor = 1.4
Cs = 0.068 F
Rs = 261 k
Cp = 3300 pf
RSET = 4.4k
(Makes ISET = 250 A)
CLK0 = 27 MHz
CLK1 = GND
CLK_SEL = 0
4
V3:V0 = 0001
0
VCXO Input
Pre-Divider
1
= 1001
VCXO
Divider
Table
Phase
Detector
0
1
Charge
Pump
VCXO
VCXO Feedback Divider
= 1000
VCXO Jitter Attenuation PLL
MR = 0
MF = 0
2
N1:N0 = 01
2
nBP1:nBP0 = 11
Master Reset
10
FemtoClock
Frequency Multiplier
11
= x 22
00
01
Output
Divider
01
10
10
11
00 = 4
11
01 = 8
10 = 12
11 = 18
Q = 74.125 MHz
OE = 1
810001BK-21
www.icst.com/products/hiperclocks.html
13
REV. A AUGUST 12, 2005