ICS10001B21 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS10001B21' PDF : 21 Pages View PDF
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
FORMULAS
CLOW =
(CL1 + CS1 + CV_LOW) · (CL2 + CS2 + CV_LOW)
(C + C + C ) + (C + C + C )
L1
S1
V_LOW
L2
S2
V_LOW
CLow is the effective capacitance due to the low varactor
capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the
TPR (Total Pull Range).
CHIGH
= (CL1 + CS1 + CV_HIGH
(CL1 + CS1 + CV_HIGH)
· (CL2 + CS2 + CV_HIGH)
+ (CL2 + CS2 + CV_HIGH)
CHigh is the effective capacitance due to the high varactor
capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the
TPR (Total Pull Range).
( ) 1
1
TPR =
–
· 106
2 · C0/C1 · (1+CLOW /C0) 2 · C0/C1 · (1+CHIGH/C0)
AbsolutePullRange (APR) = TotalPullRange – (FrequencyTolerance + FrequencyStability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were some
assumptions made. First, the stray capacitance (CS1, CS2), which
is all the excess capacitance due to board parasitic, is 4pF.
Second, the expected lifetime of the project is 5 years; hence
the inaccuracy due to aging is ±15ppm. Third, though many
boards will not require load tuning capacitors (CL1, CL2), it is
recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design. Typical values for the load tuning capacitors will range
from 0 to 4pF.
(0 + 4pF + 15.4pF) · (0 + 4pF + 15.4pF)
CLOW =
= 9.7pF
(0 + 4pF + 15.4pF) + (0 + 4pF + 15.4pF)
(0 + 4pF + 29.6pF) · (0 + 4pF + 29.6pF)
CHIGH = (0 + 4pF + 29.6pF) + (0 + 4pF + 29.6pF) = 16.8pF
( ) 1
1
TPR =
–
· 106 = 226.5ppm
2 · 220 · (1+9.7pF/4pF) 2 · 220 · (1+16.8pF/4pF)
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of ±113.25
ppm with an APR of ±58.25ppm. Many times, board designers
may select their own crystal based on their application. If the
application requires a tighter APR, a crystal with better pullability
(C0/C1 ratio) can be used. Also, with the equations above, one
can vary the frequency tolerance, temperature stability, and
aging or shunt capacitance to achieve the required pullability.
810001BK-21
www.icst.com/products/hiperclocks.html
17
REV. A AUGUST 12, 2005
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