ICS10001B21 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS10001B21' PDF : 21 Pages View PDF
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
DESCRIPTION OF THE PLL STAGES
The ICS843002-21 is a two stage device, a VCXO PLL fol-
lowed by a low phase noise FemtoClock frequency multiplier.
The VCXO uses an external pullable crystal which can be
pulled ±100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. There are two VCXO crystal
ports in order to provide VCXO frequency versatility. For HDTV
applications, this allows the use of a 26.973027MHz crystal
for the generation of 74.175MHz, or a 27.00MHz crystal for
the generation of 74.25MHz, for example.
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed device
characteristics and by other characterizes set by the user. This
includes the values of RS, CS, CP and RSET as shown in the
External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by:
NBW (VCXO PLL) =
RS x ICP x KO
2π x Feedback Divider
The VCXO output frequency can be output directly from the
device, or it can be passed to the FemtoClock frequency
multiplier which will multiply it up to a higher frequency.
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the VCXO feedback divider value (bandwidth and damping
factor), and by the external loop filter components (bandwidth,
damping factor, and 2nd frequency response). A practical range
of VCXO PLL bandwidth is from about 1Hz to about 1kHz.
The setting of VCXO PLL bandwidth and damping factor is
covered later in this document. A PC based PLL bandwidth
calculator is also under development. For assistance with loop
bandwidth suggestions or value calculation, please contact
ICS applications.
Table 3A shows frequency translation configuration examples.
Note that in the first two V3:V0 selections the VCXO PLL feed-
back divider is the same value of 1000. This means the VCXO
PLL loop response (bandwidth and damping factor) will be the
same for all of these settings.
WHERE:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps (see table on page 12)
KO = VCXO Gain in Hz/V
Feedback Divider = 1 to 11011 (as determined by inputs
V3:V0)
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by CP. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
ƒ(Phase Detector) = Input Frequency ÷ Pre-Divider)
The same is true for V3:V0 = 0010 through 0110. This means
the device can be configured to translate between 74.175MHz,
74.25MHz, and 27MHz (from any one to another, all nine com-
binations) and it will maintain the same loop response char-
acteristics. This is also true for V3:V0 = 1000 through 1010.
The PLL loop damping factor is determined by:
R
DF = x S
2
I xC xK
CP
S
O
Feedback Divider
For high VCXO PLL feedback divider values, the phase de-
tector rate, and therefore loop filter charge pulse rate, is greatly
reduced. To prevent output clock wander, low leakage capaci-
tors should be used. In addition, when loop bandwidth is low
(say below 20Hz), capacitors with low microphonic sensitiv-
ity should be used. PPS film type capacitors are one type that
perform well in this environment. Below 5Hz, shielding should
be considered to prevent excessive phase wander (low fre-
quency phase jitter or clock phase deviation).
WHERE:
C = Value of capacitor C in loop filter in Farads
S
S
810001BK-21
www.icst.com/products/hiperclocks.html
14
REV. A AUGUST 12, 2005
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