ICS10001B21 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS10001B21' PDF : 21 Pages View PDF
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS810001-21
FEMTOCLOCKS™ DUAL VCXO VIDEO PLL
EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to
ensure output stability. A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
64
LF1 1
27/30 28/31
LF0 2
CP
RS
ISET 3
CS
RSET
The best way to set the value of CP is to use the filter response
software available from ICS (please refer to the following section).
CP should be increased in value until it just starts affecting the
passband peak.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 27/30 to ground and between pins 38/31 to ground.
These are optional crystal load capacitors which can be used to
center tune the external pullable crystal (the crystal frequency
can only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response can be found at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
shouldnot run underneath the device, the loop filter or crystal
components.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be
maintained between components C and C in the loop filter:
S
P
CP
=
CS
20
CP establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of CP based on
a CS value that would be used for a damping factor of 1. This will
minimize baseband peaking and loop instability that can lead to
output jitter.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and CP is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
810001BK-21
www.icst.com/products/hiperclocks.html
15
REV. A AUGUST 12, 2005
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