IR3Y48A1
Switching Characteristics
(AVDD, DVDD = 2.7 to 3.6 V, AVSS, DVSS = 0 V, TA = –30 to +85˚C, CL < 10 pF)
PARAMETER
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNIT NOTE
Conversion frequency
fS
0.5
18 MHz
Clock cycle time
Clock rise time
Clock fall time
tCYC
55
tR
(30%/70%) AVDD, DVDD
tF
(70%/30%) AVDD, DVDD
ns
2
ns
2
ns
Clock low period
tL
23
ns
Clock high period
tH
23
ns
SHR pulse width
tWR
11
ns
SHD pulse width
tWD
11
ns
SHR sampling aperture
tDR
4
ns
SHD sampling aperture
tDD
4
ns
Data pulse setup
tSUD
2
ns
1
Data pulse hold
tHD
5
ns
Sampling pulse non-overlap
tSP
1
ns
Enable pulse setup
tSUE
10
ns
Enable pulse hold
tHE
10
ns
OUTCK setup
tSUOC
0
ns
OUTCK hold
3 state disable delay
3 state enable delay
tHOC
tDLD
tDLE
Active/High-Z
High-Z/Active
10
ns
20
ns
20
ns
tDL1
ADC output data delay
tDL2
2
ns
35 ns
NOTE :
1. When SHD› is earlier than ADCKfi, assumed positive.
(In the above table, SHD› must be earlier at least 2 ns than ADCK›.)
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