IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
NOTE :
At default condition in ADIN mode, data are sampled at the
falling edge of the ADCK clock, and are output at the rising
edge of the OUTCK clock. When the data are sampled and
are output at the falling edge of the ADCK clock, set ADCK
polarity register to "1".
(The upper figure on the previous page shows default timing,
and the lower left figure on the previous page shows inverted
timing.)
IR3Y48A1
Delay from data sampling to data output
ADCK normal : At [Mode (1) Register D6 = 0]
5.5 clk delay
ADCK inversion : At [Mode (1) Register D6 = 1]
6.0 clk delay
In ADIN input mode, the above-mentioned register setting is
available.
At ADIN (PGA) input [Mode (1) Register D5 = 0 & D4 = 1]
digital data output is delayed from above timing by 2 clk.
ADCK Clock Waveform
tH
0.7AVDD
0.3AVDD
tR
tF
tL
tCYC
29
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