IR3Y48A1
AD Conversion Timing (At ADIN (ADC) Input [Mode (1) Register D5 = 1])
ADIN : ADC Direct Input
ADCK
ADC Input
OUTCK
Falling edge
N+1
N
Sampling point
Digital
Output
N–6
N–5
N+4
0.7 AVDD
0.3 AVDD
N+5
N+6
tDL
N–2
0.7 AVDD
0.3 AVDD
N–1
N
ADCK Inversion
ADCK
Rising edge
N+1
ADC
Input
N
Sampling point
These figures are shown when the Mode (1) D8 bit
is set to "1", and an external clock is input to the
OUTCK pin. When setting D8 bit to "0", the ADCK
is used as OUTCK.
OUTCK Timing
ADCK
OUTCK
tHOC
tSUOC
28