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IS42S16128-10T View Datasheet(PDF) - Integrated Silicon Solution

Part Name
Description
MFG CO.
IS42S16128-10T
ISSI
Integrated Silicon Solution ISSI
'IS42S16128-10T' PDF : 75 Pages View PDF
IS42S16128
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data correspond-
ing to this address is output in synchronization with the
clock signal after the CAS latency period. Next, data
corresponding to an address generated automatically by
the device is output in synchronization with the clock
signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
ISSI ®
is a full page is an exception. In this case the output
buffers must be set to the high impedance state by
executing a burst stop command.
Note that upper byte and lower byte output data can be
masked independently under control of the signals ap-
plied to the U/LDQM pins. The delay period (tQMD) is fixed
at two, regardless of the CAS latency setting, when this
function is used.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
READ
I/O
tCAC
CAS LATENCY
CAS latency = 3, burst length = 4
DOUT 0 DOUT 1 DOUT 2 DOUT 3
BURST LENGTH
Burst Write
The write cycle is started by executing the command. The
address provided during write command execution is
used as the starting address, and at the same time, data
for this address is input in synchronization with the clock
signal.
Next, data is input in other in synchronization with the
clock signal. During this operation, data is written to
address generated automatically by the device. This
cycle terminates automatically after a number of clock
cycles determined by the stipulated burst length. How-
ever, the case where the burst length is a full page is an
exception. In this case the write cycle must be terminated
by executing a burst stop command.
CLK
The latency for I/O pin data input is zero, regardless of the
CAS latency setting. However, a wait period (write recov-
ery: tDPL) after the last data input is required for the device
to complete the write operation.
Note that the upper byte and lower byte input data can be
masked independently under control of the signals ap-
plied to the U/LDQM pins. The delay period (tDMD) is fixed
at zero, regardless of the CAS latency setting, when this
function is used.
The selected bank must be set to the active state before
executing this command.
COMMAND WRITE
I/O DIN 0
DIN 1
DIN 2
DIN 3
BURST LENGTH
CAS latency = 2,3, burst length = 4
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
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