IS42S16128-10T View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

MFG CO.

IS42S16128-10T

128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

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IS42S16128

ISSI ®

Interval Between Read and Write Commands

A read command can be interrupted and a new write

command executed while the read cycle is in progress,

i.e., before that cycle completes. Data corresponding to

the new write command can be input at the point new write

command is executed. To prevent collision between

input and output data at the I/On pins during this opera-

tion, the

output data must be masked using the U/LDQM pins. The

interval (tCCD) between these commands must be at least

one clock cycle.

The selected bank must be set to the active state before

executing this command.

CLK

COMMAND

tCCD

READ A0 WRITE B0

U/LDQM

HI-Z

I/O

DIN B0 DIN B1 DIN B2

READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)

CAS latency = 2, 3, burst length = 4

DIN B3

Integrated Silicon Solution, Inc. — 1-800-379-4774

27

Rev. A

03/13/00

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