IS42S16128-10T View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
MFG CO.
IS42S16128-10T
Integrated Silicon Solution
'IS42S16128-10T' PDF : 75 Pages View PDF
IS42S16128
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16128 can output data continuously from the
burst start address (a) to location a+255 during a read
cycle in which the burst length is set to full page. The
IS42S16128 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (tRAS max.) following the burst stop
command.
ISSI ®
After the period (tRBD) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance state.
This period (tRBD) is one clock cycle when the CAS latency
is one, two clock cycle when the CAS latency is two and
three clock cycle when the CAS latency is three.
CAS Latency
tRBD
3
2
3
2
CLK
COMMAND READ A0
tRBD
BST
I/O
DOUT A0 DOUT A0 DOUT A1 DOUT A2 DOUT A3
HI-Z
READ (CA=A, BANK 0)
CAS latency = 2, burst length = full page
BURST STOP
CLK
COMMAND READ A0
BST
tRBD
I/O
READ (CA=A, BANK 0)
CAS latency = 3, burst length = full page
DOUT A0 DOUT A0 DOUT A1 DOUT A2 DOUT A3
HI-Z
BURST STOP
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
Share Link: 