LH28F320BFHE-PBTLZ2 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F320BFHE-PBTLZ2' PDF : 36 Pages View PDF
LHF32FD2
27
1.2.6 Reset Operations
VIH
RST# (P)
VIL
DQ15-0
(D/Q)VOH
VOL
RST# (P) VIH
VIL
DQ15-0 (D/Q)VOH
VOL
tPHQV
High Z
tPLPH
(A) Reset during Read Array Mode
tPLRH
SR.7="1"
ABORT
COMPLETE
tPHQV
High Z
tPLPH
(B) Reset during Erase or Program Mode
VALID
OUTPUT
VALID
OUTPUT
VCC(min)
VCC
GND
VIH
RST# (P)
VIL
DQ15-0
(D/Q)VOH
VOL
t2VPH
tVHQV
tPHQV
High Z
(C) RST# rising timing
VALID
OUTPUT
Figure 11. AC Waveform for Reset Operations
Reset AC Specifications (VCC=2.7V-3.6V, TA=-40°C to +85°C)
Symbol
Parameter
Notes
Min.
Max.
Unit
tPLPH
RST# Low to Reset during Read
(RST# should be low during power-up.)
1, 2, 3
100
ns
tPLRH
RST# Low to Reset during Erase or Program
1, 3, 4
22
µs
t2VPH
VCC 2.7V to RST# High
1, 3, 5
100
ns
tVHQV
VCC 2.7V to Output Delay
3
1
ms
NOTES:
1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Rev. 2.44
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