LH28F800BJB-PTTL90 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F800BJB-PTTL90' PDF : 47 Pages View PDF
LHF80J21
36
6.2.5 AC Characteristics - Write Operations(1)
Sym.
VCC=2.7V-3.6V, TA=0°C to +70°C
Parameter
Notes
Min.
Max.
Unit
tAVAV Write Cycle Time
90
ns
tPHWL RP# High Recovery to WE# Going Low
2
1
µs
tELWL CE# Setup to WE# Going Low
10
ns
tWLWH WE# Pulse Width
50
ns
tSHWH WP#VIH Setup to WE# Going High
2
100
ns
tVPWH VCCW Setup to WE# Going High
2
100
ns
tAVWH Address Setup to WE# Going High
3
50
ns
tDVWH Data Setup to WE# Going High
3
50
ns
tWHDX Data Hold from WE# High
0
ns
tWHAX Address Hold from WE# High
0
ns
tWHEH CE# Hold from WE# High
10
ns
tWHWL WE# Pulse Width High
30
ns
tWHRL WE# High to RY/BY# Going Low or SR.7 Going "0"
100
ns
tWHGL Write Recovery before Read
0
ns
tQVVL VCCW Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVSL WP# VIH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tFVWH BYTE# Setup to WE# Going High
5
50
ns
tWHFV BYTE# Hold from WE# High
5
90
ns
NOTES:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are
the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VCCW should be held at VCCWH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit
configuration success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.27
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