LH28F800BJB-PTTL90 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F800BJB-PTTL90' PDF : 47 Pages View PDF
LHF80J21
38
6.2.6 Alternative CE#-Controlled Writes(1)
Sym.
VCC=2.7V-3.6V, TA=0°C to +70°C
Parameter
Notes
Min.
Max.
Unit
tAVAV Write Cycle Time
90
ns
tPHEL RP# High Recovery to CE# Going Low
2
1
µs
tWLEL WE# Setup to CE# Going Low
0
ns
tELEH CE# Pulse Width
50
ns
tSHEH WP#VIH Setup to CE# Going High
2
100
ns
tVPEH VCCW Setup to CE# Going High
2
100
ns
tAVEH Address Setup to CE# Going High
3
50
ns
tDVEH Data Setup to CE# Going High
3
50
ns
tEHDX Data Hold from CE# High
0
ns
tEHAX Address Hold from CE# High
0
ns
tEHWH WE# Hold from CE# High
0
ns
tEHEL CE# Pulse Width High
30
ns
tEHRL CE# High to RY/BY# Going Low or SR.7 Going "0"
100
ns
tEHGL Write Recovery before Read
0
ns
tQVVL VCCW Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVSL WP# VIH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tFVEH BYTE# Setup to CE# Going High
5
50
ns
tEHFV BYTE# Hold from CE# High
5
90
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration.
4. VCCW should be held at VCCWH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit
configuration success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.27
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