LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
TIMING DIAGRAMS (cont’d)
Enhanced Operating Mode Timing Diagram
WCLK
D0 - D17
NO WRITE
tSKEW11
NO WRITE
B
tDS
DATA WRITE
tHFS
tSKEW11
tDS
DATA WRITE
tHFS
tHFS
HF
WEN
RCLK
A
tENS
tENH
C
tENS
tENH
REN
OE
LOW
tA
Q0 - Q17
DATA IN
OUTPUT REGISTER
DATA READ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a
rising WCLK edge for HF to change predictably during the current
clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW1, then it is not guaranteed
that HF will change state until the next following WCLK edge.
2. The internal state of the FIFO:
At A , exactly half full.
At B , half+1 words.
At C , exactly half full again.
tA
NEXT
DATA READ
Figure 19. Half-Full-Flag Timing, When Synchronized
to Input Port (Enhanced Operating Mode)
540235-25
32
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