LH540245U-20 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

MFG CO.

LH540245U-20

2048 × 18 / 4096 × 18 Synchronous FIFOs

Sharp Electronics 

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2048 x 18/4096 x 18 Synchronous FIFOs

TIMING DIAGRAMS (cont’d)

Enhanced Operating Mode Timing Diagram

A

WCLK

tDS

D0 - D17

DATA WRITE 1

tENS

tENH

WEN

RCLK

tSKEW2(1)

B

tHFS

HF

tENS tENH

REN

C

tDS

DATA WRITE 2

tENH

tENS

tSKEW2(1)

tHFS

OE

LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

NOTE:

1. tSKEW2 is the minimum time between a rising WCLK edge and a

rising RCLK edge for HF to change predictably during the current

clock cycle. If the time between the rising edge of WCLK and the

rising edge of RCLK is less than tSKEW2, then it is not guaranteed

that HF will change state until the next following RCLK edge.

2. The internal state of the FIFO:

At A , half+1 words.

At B , exactly half full.

At C , half+1 words again.

DATA READ

Figure 20. Half-Full-Flag Timing, When Synchronized

to Output Port (Enhanced Operating Mode)

LH540235/45

tHFS

540235-26

33

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