LH540245U-20 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

MFG CO.

LH540245U-20

2048 × 18 / 4096 × 18 Synchronous FIFOs

Sharp Electronics 

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2048 x 18/4096 x 18 Synchronous FIFOs

TIMING DIAGRAMS

tRS

RS

tRSS

tRSR

REN, WEN, LD

tRSF

EF, PAE

tRSF

FF, PAF, HF

tRSF

Q0 - Q17

OE = HIGH1

OE = LOW

NOTES:

1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance state if OE = HIGH.

2. The clocks (RCLK, WCLK) may be free-running during a reset operation.

Figure 6. Reset Timing

WCLK

D0 - D17

WEN

FF

tCLKH

tCLK

tCLKL

tWFF

tSKEW1(1)

tDS

tDH

VALID

DATA IN

tENS

tENH

NO OPERATION

tWFF

RCLK

REN

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a

rising WCLK edge for FF to change predictably during the current

clock cycle. If the time between the rising edge of RCLK and the

rising edge of WCLK is less than tSKEW1, then it is not guaranteed

that FF will change state until the next following WCLK edge.

Figure 7. Synchronous Write Operation

LH540235/45

540235-5

540235-6

21

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